1. Field of the Invention
The present invention relates generally to a mechanism for positioning semiconductor wafers used for processing wafers and, more particularly, a positioning mechanism for a semiconductor wafer, having a notch on the periphery thereof, for setting the notch position in a predetermined radial direction. In manufacturing semiconductor integrated circuits, especially in wafer processes, semiconductor wafers having a plurality of integrated circuit patterns formed thereon and being processed in order, are required to be positioned in a fixed direction. The positioning mechanism of the present invention is particularly effective in positioning a plurality of wafers put in a wafer carrier in the fixed direction.
2. Description of the Related Art
Generally, it is known to provide a cut off portion formed in a circular semiconductor wafer. The cut off portion has a segmental shape formed by an arc and a chord. The remaining flat side surface of the wafer formed by the cutoff is usually called an "orientation flat" which is formed in a specified direction with regard to an orientation of a semiconductor crystal. The orientation flat is conveniently used for the purpose of positioning wafers, and is formed at an early stage by removing a side portion of a semiconductor ingot parallel to the axis thereof after the cylindrical ingot is grown. The semiconductor wafers with the orientation flat are obtained by cutting the ingot into slices.
Wafers are usually carried or handled in a container, (in other words, a "carrier" of semiconductor wafers) during wafer process, or before and after the specific wafer process in which each wafer is processed one by one. Therefore, it is important to position or to realign plural wafers in the carrier in a fixed direction in order to make the wafer process progress efficiently.
In lithography or test processes of semiconductor wafers, in which each wafer is processed individually, the orientation flat is generally utilized as a reference plane in positioning the wafer precisely at a predetermined position by moving a stage of the apparatus used therefor. To improve work efficiency for these processes, it is necessary to perform a pre-alignment procedure of wafers in the carrier.
In the past, the wafer positioning in the carrier has been performed mechanically using the orientation flat. For a brief explanation, reference is made to FIGS. 1(a) and 1(b). A semiconductor wafer 5 has an orientation flat 9, a straight flat portion thereof having a length ranging between about 30 mm and 50 mm. Generally, the dimensions are standardized, depending on wafer size. The wafer 5 is contained in the carrier and supported vertically and rotatably. For positioning the wafer 5, it is mounted on a drive roller 2, which is rotated by a drive mechanism (not shown). When the circular periphery of the wafer 5 is mounted on the roller 2, a small gap is formed between a wafer guide 11 and the wafer periphery. Thus, the wafer 5 easily rotates in a direction shown by the directional arrow. When the orientation flat 9 rotates to the bottom position, the wafer seats on the wafer guide 11 and stops rotating. When a carrier containing a plurality of wafers and having sufficient length is positioned on the drive roller 2 and the drive roller 2 is rotated, all wafers are positioned at one time by the single drive mechanism.
The above method has a problem in that the accuracy of alignment is not good; therefore, an improvement is disclosed in Japanese Unexamined Patent Publication "SHO-62-219535" opened on Sept. 26, 1987 by T. Ohno.
In recent years, there has been a trend to use a wafer configuration having a notch instead of an orientation flat. The notched wafer is more economical because a larger area is available for forming integrated circuit chips than the case for wafers with the orientation flat. Moreover, the orientation flat has a negative influence on uniformity in processing wafers. However, the notched area is so small compared with the cut off portion of the orientation flat that the simple positioning mechanism such as shown in FIGS. 1(a) and 1(b) can not be used for notched wafers.